1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating the same and, more particularly, to semiconductor device suitably applicable to a nonvolatile semiconductor memory in which a floating gate and a control gate are formed via a dielectric film.
2. Description of the Related Art
Recently, a nonvolatile memory such as an EEPROM which holds stored data even when disconnected from a power supply has attracted attention as a semiconductor memory. In this nonvolatile memory, a floating gate is formed on a semiconductor substrate via a tunnel insulating film, and a control gate is so formed as to oppose this floating gate via a dielectric film.
One example of this nonvolatile semiconductor memory is disclosed in Japanese Patent Laid-Open No. 6-85279. This element is obtained by turning the above nonvolatile semiconductor memory upside down. More specifically, this nonvolatile semiconductor memory is fabricated by sequentially stacking a gate insulating film, a floating gate, and a tunnel insulating film in an insulating film formed on a semiconductor substrate, and forming a semiconductor layer having a source and a drain on top of the resultant structure. Since contacts can be extracted from the upper surface side, this element facilitates arranging word lines and is suited to increase the degree of integration.
The structure, however, of this nonvolatile semiconductor memory is complicated because the memory has a stacked gate structure, and this extremely increases the accuracy requirements when the element is to be formed. In addition, to lower the write voltage, it is necessary to increase the area of the overlap of the control gate and the floating gate. This not only increases the number of fabrication steps and the fabrication cost and lowers the reliability but also interferes with an increase in the degree of integration.
To solve the above problems, Japanese Patent Laid-Open No. 59-155968 or Japanese Patent Publication No. 7-112018 has disclosed an EEPROM which has a small cell area and includes a single-layer polysilicon film. This EEPROM includes a first element active region formed by forming a source and a drain on a semiconductor substrate and a second element active region formed adjacent to the first element active region via an element isolation structure by forming an impurity diffusion layer. A single-layer polysilicon film is patterned to form a floating gate which is formed by patterning on a channel between the source and the drain via a tunnel insulating film in the first element active region. This floating gate is so formed by patterning to oppose the impurity diffusion layer via a gate insulating film in the second active region. The impurity diffusion layer in the second element active region functions as a control gate.
In the above single-layer gate EEPROM, however, it is necessary to apply a high voltage of 20 (V) or more to the control gate, i.e., the impurity diffusion layer when data is erased or written, especially when data is erased. Consequently, an enough breakdown voltage becomes difficult to ensure between the control gate and the semiconductor substrate, leading to a serious problem of an operation error.
Furthermore, Japanese Patent Laid-Open No. 7-147340 has disclosed an EEPROM which has a diffusion layer serving as the control gate separated from other semiconductor area to apply a high voltage to the diffusion layer.
However, it is difficult to minimize variations in the threshold value of the EEPROM and stably perform write and read operations.
It is an object of the present invention to provide a reliable semiconductor device which is a single-layer gate semiconductor device by which a low-cost process is possible, has a control gate which can well withstand a high voltage applied when data is erased or written, and can prevent an operation error, and a method of fabricating the same.
A semiconductor device of the present invention is a semiconductor device comprising a semiconductor substrate in which a first and a second element active regions are demarcated by means of element isolation structure, said structure having a shield plate electrode formed on said semiconductor substrate via a first insulating film, a first and a second conductive regions formed on a surface region of the semiconductor substrate in the first element active region, a first electrode formed on the semiconductor substrate between the first and the second conductive regions via a second insulating film, a third conductive region formed in the surface region of the semiconductor substrate in the second element active region, and a second electrode formed on the third conductive region via a dielectric film, wherein said first electrode and the second electrode are electrically connected.
Another aspect of the semiconductor device of the present invention is a semiconductor device comprising a semiconductor substrate in which a first and a second element active regions are demarcated by means of element isolation structure, a first and a second conductive regions formed on a surface region of the semiconductor substrate in the first element active region, a first electrode formed on the semiconductor substrate between the first and the second conductive regions via a second insulating film, a third conductive region formed in the surface region of the semiconductor substrate in the second element active region, and a second electrode formed on the third conductive region via a dielectric film, wherein said first electrode and the second electrode are electrically connected and a third electrode is connected to the semiconductor substrate to impress a predetermined electric potential to the semiconductor substrate in said first element active region.
A method of fabricating a semiconductor device of the present invention comprises the first step of defining first, second, third, and fourth element active regions by forming an element isolation structure on a semiconductor substrate having an insulating layer in a predetermined depth and covering a region from side surfaces to a lower surface of at least said first element active region with said insulating layer and said element isolation structure the second step of forming a first diffusion layer by doping an impurity into said first element active region, the third step of forming a diffusion layer region by doping an impurity having a conductivity type opposite to a conductivity type of said semiconductor substrate into a surface region of said semiconductor substrate in said second element active region, the fourth step of forming first, second, third, and fourth insulating films on said semiconductor substrate in said first, second, third, and fourth element active regions, respectively, the fifth step of forming a conductive film via first, second, third, and fourth insulating films on an entire surface of said semiconductor substrate in said first, second, third, and fourth element active regions, respectively, the sixth step of patterning said conductive film to leave a predetermined pattern in at least one of said first and third element active regions and form gate electrodes in said second and fourth element active regions, the seventh step of doping an impurity into said third and fourth element active regions to form a pair of second diffusion layers and a pair of third diffusion layers in surface regions of said semiconductor substrate on two sides of said conductive film in said third and fourth element active regions, the eighth step of doping an impurity having a conductivity type opposite to a conductivity type of said diffusion layer region into said second element active region to form a pair of fourth diffusion layers in surface regions of said semiconductor substrate on two sides of said conductive film in said second element active region, the ninth step of forming a fifth diffusion layer by doping an impurity into said semiconductor substrate near said third element active region, and the 10th step of forming an electrode connected to said fifth diffusion layer to apply a predetermined voltage to said third element active region via said fifth diffusion layer.
Another aspect-of the method of fabricating a semiconductor device of the present invention comprises the first step of defining first and second element active regions by forming an element isolation structure on a semiconductor substrate having an insulating layer in a predetermined depth and covering a region from side surfaces to a lower surface of at least said first element active region with said insulating layer and said element isolation structure, the second step of forming a first diffusion layer by doping an impurity into a surface region of said semiconductor substrate in said first element active region, the third step of forming a first insulating film on said semiconductor substrate in said first element active region and a second insulating film on said semiconductor substrate in said second element active region, the fourth step of forming a conductive film on an entire surface including said first and second element active regions and patterning said conductive film to leave a predetermined pattern in at least one of said first and second element active regions, the fifth step of doping an impurity into an entire surface including said second element active region to form a pair of second diffusion layers in surface regions of said semiconductor substrate on two sides of said conductive film in said second element active region, the sixth step of forming a third diffusion layer by doping an impurity into said semiconductor substrate near said second element active region, and the seventh step of forming an electrode connected to said third layer to apply a predetermined voltage to said second element active region via said third diffusion layer.
Still another aspect of the method of fabricating a semiconductor device of the present invention comprises the first step of forming a first trench in a surface of a nearly flat semiconductor region, the second step of forming a first film having a film thickness lager than a depth of said first trench on an entire surface of said semiconductor region to bury said first trench, the third step of forming a second trench in a portion of said first film above said first trench, said second trench being formed to make a bottom surface of said second trench lower than said semiconductor substrate except for said first trench and not to reach the surface of said semiconductor substrate in said first trench, the fourth step of forming a second film having a film thickness larger than a depth of said second trench on an entire surface of said first film to bury said second trench, and the fifth step of polishing at least said first and second films by using said semiconductor substrate as a stopper, thereby planarizing the surface.
Still another aspect of the method of fabricating a semiconductor device of the present invention comprises the first step of forming a first insulating film on a semiconductor substrate, the second step of doping a first impurity to form a first diffusion layer in a predetermined range of a surface region of said semiconductor substrate, the third step of forming a first conductive film on said first insulating film, the fourth step of selectively removing said first conductive film until said first insulating film is exposed, thereby forming a first island conductive film on said first diffusion layer and a shield plate electrode having a first hole and a second hole which surrounds said first island conductive film and is wider than said first diffusion layer, the fifth step of forming a second insulating film on an entire surface to bury said first island conductive film and said shield plate electrode, the sixth step of defining an element active region by removing said second insulating film and said first insulating film present in said first hole until said semiconductor substrate is exposed, the seventh step of sequentially stacking a third insulating film and a second conductive film on said semiconductor substrate in said element active region, the eighth step of selectively removing said second conductive film to form a second island conductive film via said third insulating film on said semiconductor substrate in at least said element active region, the ninth step of doping a second impurity into an entire surface including said element active region to form a pair of second diffusion layers in surface regions of said semiconductor substrate on two sides of said second island conductive film in said element active region, and the 10th step of forming an integrated floating gate electrode by electrically connecting said first and second island conductive films.
Still another aspect of the method of fabricating a semiconductor device of the present invention comprises the first step of forming a first insulating film on a semiconductor substrate, the second step of doping a first impurity to form a first diffusion layer in a predetermined range of a surface region of said semiconductor substrate, the third step of forming a first conductive film on said first insulating film, the fourth step of selectively removing said first conductive film until said first insulating film is exposed, thereby forming a first island conductive film on said first diffusion layer and a shield plate electrode having a first hole and a second hole which surrounds said first island conductive film and is wider than said first diffusion layer, the fifth step of forming a second insulating film on an entire surface to bury said first island conductive film and said shield plate electrode, the sixth step of defining an element active region by removing said second insulating film and said first insulating film present in said first hole until said semiconductor substrate is exposed, the seventh step of forming a third insulating film on said semiconductor substrate in said element active region, the eighth step of forming a hole which exposes said first island conductive film in said second insulating film, the ninth step of filling said hole by forming a second conductive film on an entire surface including said element active region, the 10th step of selectively removing said second conductive film so as to leave a pattern extending from said hole to said element active region, thereby forming a floating gate electrode integrated with said first island conductive film, and the 11th step of doping a second impurity into said element active region to form a pair of second diffusion layers in surface regions of said semiconductor substrate on two sides of said second conductive film in said element active region.
Still another aspect of the method of fabricating a semiconductor device of the present invention comprises the first step of forming a first insulating film in a predetermined region on a semiconductor substrate and a second insulating film on said semiconductor substrate not covered with said first insulating film, the second step of doping a first impurity to form a first diffusion layer in a surface region of said semiconductor substrate below said second insulating film, the third step of forming a first conductive film on said first and second insulating films, the fourth step of selectively removing said first conductive film until said first or second insulating film is exposed to form a first island conductive film on said first diffusion layer and a second island conductive film on said first insulating film, and simultaneously forming a shield plate electrode having holes surrounding said first and second island conductive films, the fifth step of forming a floating gate electrode by electrically connecting said first and second island conductive films, and the sixth step of doping an impurity into said hole surrounding said second island conductive film to form a pair of second diffusion layers in surface regions of said semiconductor substrate on two sides of said second island conductive film.
In the present invention, a conductor layer which functions as the control gate of a nonvolatile semiconductor memory is formed in a surface region of a semiconductor substrate, and a region from the side surfaces to the lower surface of this conductor layer is completely covered with an insulating film. Therefore, even when a high voltage is applied to the control gate to erase data, a high breakdown voltage can be held in the outer portion of the conductor layer. Also, a pair of diffusion layers are formed in surface regions of the semiconductor substrate on the two sides of a tunnel oxide film of the nonvolatile semiconductor memory, and an electrode is formed to apply a predetermined substrate potential to an element active region including these diffusion layers. Accordingly, it is possible to minimize variations in the threshold value and stably perform write and read operations.
The present invention can realize a reliable semiconductor device which is a single-layer gate semiconductor device by which a low-cost process is possible, has a control gate which can well withstand a high voltage applied when data is erased or written, and can prevent an operation error.